1. Field of the Invention
The present invention generally relates to semiconductor memories and to methods of refreshing memory cells of semiconductor memories. More particularly, the present invention relates to semiconductor memories having variable memory sizes and to methods of refreshing memory cells of such memories.
2. Description of the Related Art
Variable sized semiconductor memory devices are known in which all or a subset of the memory blocks contained in the devices can be selectively utilized. One such memory device is the Uni-transistor RAM (UtRAM), also known as the Psuedo SRAM (PSRAM), which is configured of DRAM cells but has an SRAM interface. For example, a 16 mega-bit (16M) UtRAM operating in a full memory mode can function like a 16M SRAM, whereas the same 16M UtRAM operating in a half memory mode can function like an 8M SRAM.
Largely for cost reasons, it is sometimes preferable to implement an 8M SRAM using a 16M UtRAM operating in the half memory mode. Also, as already suggested, the UtRAM allows for flexibility in setting the memory size. Varying the size/capacity of the UtRAM is known as “reduced memory size mode” (RMS mode). The RMS mode can be established at any time during the operation of the memory device.
Since the UtRAM contains DRAM cells, the memory cells must be periodically refreshed to maintain the integrity of stored data. As is best explained by way of example, this refresh requirement creates a problem when the RMS mode is used. Assume that the UtRAM contains two memory blocks, where both memory blocks are used in a full memory mode, and only one memory block is used in a half memory mode. Assume further that four word lines (designated 0, 1, 2 and 3) are arranged in the first memory block, and four more word lines (designated 4, 5, 6 and 7) are arranged in the second memory block. In the refresh operation of the full memory mode, the word lines are sequentially selected in order (0 through 7). This is illustrated on the left side of the vertical line extending through the timing chart of FIG. 1. As shown in the first pulse waveform, the word lines are selected one-by-one in order (0, 1, 2, 3, 4, 5, 6, 7) during each of successive refresh periods T. The total design refresh cycle time is 8T.
Still referring to the top pulse waveform of FIG. 1, assume that the memory device changes to the half memory mode after the last word line (7) is selected during the refresh operation. As illustrated to the right of the vertical line, only half the word lines (0, 1, 2, 3) are selected one-by-one in order during the half memory mode. Note that each successive selection takes place at 2T intervals. This is because design restrictions mandate that the total refresh cycle time remain at 8T. A problem arises in this case because the effective refresh cycle time for the fourth word line (3) is 12T during the transition between memory modes. This exceeds the design refresh cycle time of 8T, meaning that data contained in the memory cells of the fourth word line can be lost.
The remaining pulse waveforms of FIG. 1 respectively represent the seven other possible instances in which the memory device can be switched to the half memory mode. As can be seen in the figure, there are multiple cases in which the effective refresh cycle time of a given word line exceeds the design refresh cycle time of 8T.
As shown in FIG. 2, this problem also arises when switching from the half memory mode to the full memory mode. For example, as illustrated by the top pulse waveform of FIG. 2, if the memory mode is switched from half to full after selecting the fourth word line (3), the effective refresh cycle time for the first word line (0) becomes 12T. Again, this exceeds the design refresh period of 8T.